The present invention relates to complementary metal oxide semiconductor field effect transistor (CMOSFET) circuit topology and, in particular, a floating body CMOSFET inverter configuration having controllable logic state transition delay time.
As Moore""s Law continues to drive the demand for faster computers and more highly-packed dense integrated circuit (IC) configurations, there is an increasing desire for circuit devices and topologies having lower power consumption and supply voltage requirements while increasing switching speed performance. Bulk CMOS technology has generally been able to increase overall switching speeds as well as reducing power and voltage requirements with decreasing circuit geometries to accommodate more densely packed IC chips.
One limitation of CMOS technology, however, which effects the overall switching speed, is the inherent parasitic capacitance usually found between drain and substrate or source and substrate. This capacitance typically consists of two components: the first component is the capacitance between the drain/source and the substrate or body; the other component is the capacitance between the drain/source and the channel-stop implant located under the field oxide region of the device. When switching between states, this capacitance generally must either discharge or charge before the device can complete state transition. The time required for this charging or discharging typically delays the overall switching speed of the device.
In silicon on insulator (SOI) devices, the substrate and body terminals are fully isolated dielectrically from the drain/source by a film of oxide traversing the device. This oxide, called the buried oxide, typically separates the body from the drain/source, and, because it traverses the device, removes the channel-stop implant found in regular bulk CMOS devices. Without the channel-stop, the overall drain/source-to-body capacitance is generally reduced to only the single component of drain/source-to-body capacitance. The lower overall capacitance, thus, increases the switching speeds of SOI architecture devices.
In addition to the reduced drain/source-to-body capacitance in SOI devices, speed and power consumption are usually further enhanced by allowing the substrate or body connection to float. The floating body configuration also beneficially allows construction of SOI devices using less chip area. While the floating body connection diminishes delay time, power consumption, and device area, there are a number of detrimental effects associated with this configuration.
Because the body is not connected at any certain point on the MOSFET device, body voltage will generally vary depending on the following conditions: the bias condition of the device; the capacitive coupling between the gate, source, drain, and body voltages; carrier generation (holes in nMOSFET, electrons in pMOSFET) caused by impact ionization; and the rate of generation/recombination in the space charge layer. The variation of the body voltage creates variations in the drain/source-to-body voltage, which, in turn, may lead to variations in the device threshold voltage. Variations in the threshold voltage of any FET device generally leads to unpredictable device operation. For example, a device configured to turn on at 2 volts may not turn on at all if the threshold voltage changes to a value greater than 2 volts. Conversely, a device configured to turn off at 0.3 volts may inadvertently turn on if the threshold voltage changes by a discernable value. This could have devastating and dangerous effects depending on the application of the device.
Another detrimental effect of the floating body is typically manifested in the activation of the parasitic bipolar transistor inherent in MOSFET devices. In a typical MOSFET, the areas of the source, body, and drain form a bipolar-type relationship (xe2x80x98npnxe2x80x99 in nMOSFET devices; xe2x80x98pnpxe2x80x99 in pMOSFET devices). When the body is connected to ground or to the source or drain of the MOSFET, the drain/source-to-body voltage is such that the parasitic bipolar transistor usually remains off. However, in the floating body configuration found in SOI devices, the drain/source-to-body voltage may rise high enough to activate the bipolar transistor. Once activated, current will generally begin to flow through the bipolar device which may adversely effect, or at least create unpredictable effects on, the performance of the MOSFET.
In order to overcome these detrimental effects, body ties or body contacts have typically been fabricated into the devices to provide a direct connection between the body and one or another of the device terminals. These connections set the bias of the substrate or body, thus creating a predictable, if not fixed, drain/source-to-body voltage. However, these solutions typically negate the majority of the beneficial effects of the SOI architecture. For instance, the incorporation of body ties or body contacts generally increase the overall power consumption and propagation delay of the corresponding devices.
Logic inverters manufactured using the SOI CMOSFET architecture attempt to take advantage of the benefits of the faster switching speeds. However, these inverters exhibit history dependent delay, which is the variation in switching delay time caused by the variations in the SOI device""s threshold voltages. As noted above, the floating body configuration of SOI MOSFET devices generally causes their drain/source-to-body voltage to vary, which, in turn, causes the variations in threshold voltage. With logic inverters, it is generally preferred to have a predictable or minimal delay in order to properly configure the circuit for operation. In order to ensure proper operation of SOI-based logic inverters, the SOI MOSFETs are usually modeled in the slowest state. In operation, the typical SOI MOSFET inverter delay will inconsistently vary between its shortest and longest times. While these circuit designs experience some measured improvement over the bulk architecture CMOS, there has not been a workable solution to negate the history dependent delay or even to control or minimize it.
It would, therefore, be desirable to have an inverter circuit manufactured using SOI CMOSFET devices, which includes the ability to control or even minimize the history dependent delay typical of SOI inverters.
The present invention is directed to a system and method for complementary metal oxide semiconductor field effect transistor (CMOSFET) inverters having a floating-body terminal, comprising a p-channel FET (pFET), and an n-channel FET (nFET), wherein the pFET and nFET are connected gate terminal-to-gate terminal and drain terminal-to-drain terminal. The inverter input is connected to the gate terminals of the pFET and nFET, while the inverter output is connected to the drain terminals of the pFET and nFET. The inverter preferably has at least one body biasing inverter having an input connected to the inverter input and an output connected to both the pFET""s and nFET""s body terminal.
The inverter""s delay time can be manipulated by preferably connecting the inputs of the biasing logic inverters to the inverter input and preferably connecting the outputs of each of the biasing logic inverters included to the body terminals of each of the FET devices making up the floating-body CMOSFET inverter. In order to minimize the delay time, an odd number of biasing logic inverter stages are preferably added to the floating-body CMOSFET inverter, while maximizing the delay time is implemented by preferably adding an even number of biasing logic inverter stages.
Tying the body terminals of the CMOSFET inverter to a stable voltage source preferably diminishes the detrimental floating body effects. In the delay minimization configuration with an odd number of biasing inverter stages, the biasing inverters preferably set the pFET of the main inverter to the slowest state, while preferably setting the nFET of the main inverter to the fastest switching state. Similarly, in the delay maximization configuration with an even number of biasing inverter stages, the biasing inverters preferably set the pFET of the main inverter to the fastest state, while preferably setting the nFET of the main inverter to the slowest switching state. These stable voltages therefore overcome the history dependent delay inherent in floating body inverters such as SOI-constructed CMOSFET inverters.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention.